Not a stupid question - I have a CPLD in there to do the 1.8  <--> 3.3v translation and to allow me to do things like pin-swapping in case I stuffed the PCB up

What you use for 0.8 vdd ? I had huge problems with some regs. Everything was fine when mesaure voltages but hole thing was not working at all.

Cheers,

Ohh, my "whole thing" is working now  i am just sharing information here if i can help somehow.

I am waiting 2nd version pcb's to arrive. I will post some pics here when i finish everything. And i hope that everything will work 

I'm glad one of us is having better luck - my rpi ate my CPLD and I seem to have melted the board reworking it

Time to build another and pop it in the toaster oven I think!

I blew up my 1st board by stupidly hooking up my rpi back to front and sending 5v somewhere it should never have gone!

Assembled and reflowed another prototype tonight, and the reset sequence seems to be doing something - not getting any sensible SPI out but current draw shoots up and I seem to have reset sequence coming out the end of the chain. MISO from 1st chip isn't doing anything though

More debugging required tomorrow.

vs3 - thanks for open sourcing your project, I haven't looked at your thread yet, but I'm sure it will be a good read!

Why do you have two chips for level shifting and what are they (can't see from the picture)?
For SCK and MOSI a resistor divider should be enough for single bank/chip. Also instead of the blue wires couldn't you just swap the wires going to the RPi at the top left of the board?

P.S. I have just uploaded another change to my fork which adds support to level shifters with active low for the OE too (like TI SN74AVC4Txxx).
The next step is support for line decodes for the OE (2:4, 3:8 or 4:16) - this way you can have (for example) 8 separate banks with just 3 GPIO's from RPi by simply using 74HC138 or 74HC238 depending on the level shifter in use

For chaining you just connect 2nd chip to 1st chip without level shifters. The whole chain runs at 1.8V, and you only need to convert to 3.3V between first chip and host.

I'm not trying to do banks, my board is a single chip development board, main purpose: learn to use Altium. 2nd purpose: a board to experiment with (hardware and software) so I can make larger more sophisticated boards in the future.

cscape is of course 100% right, but hey, I work on these things late at night after the kids are asleep... so level shifters: if one is good, then two must be better. Also, you could make an argument that when driving board-to-board 3.3V has a better noise margin than 1.8V.

Anyways, all moot points as this version of the board will never get fabbed again, and it has met several goals, one of which is proving out the power supply design.

Fun discussion, you guys would be no fun in a design review ;-p

-a[g

That was my plan with the CPLD - 1.8v I/O within each board, 3.3v between them and the controller board.

Unfortunately I didn't think through the implications of powering the rpi independently of the 3.3v to the board during bring up - I wanted to be able to measure the board's 3.3v draw. Unfortunately if you power the rpi up before the board, you send 3.3v into an unpowered I/O pin on the CPLD and the chip goes into latchup

I would have liked to have c-scape in my design review to say 'you don't want to do it like that!'