Thanks a lot 'orama! 

Guy's, just been pinged an email advising 'jailcode' (where mentioned) = RTL code.

http://www.edaboard.com/thread252148.html

http://www.asic-world.com/verilog/intro1.html#Register-Transfer_Level

http://images.elektroda.net/70_1337448255.png

That will be answered in the next bit; Retro 72's Q&A, which I'm now soo happy I decided to pry further into detail. Cannot wait to start/stop every fifteen seconds transcribing. Joy!

idee,

I take it to mean firmware, but since bitcoinorama can answer that with conversations with KnC, we shall all know.
_{(my bet is that KnC intentionally lowered the specs to ensure their product is solid)}

Optimization means higher gate density, but then you have higher power supply and cooling requirement, components easier to fail. I would prefer many low temp low power devices instead of a single high power high temp device

BFL's 65 nm chip is 4GH per chip, kncminer claim a 23nm chip with 7.3GH per chip, double the efficiency, reasonable and still quite high energy density

Been a long time since I worked in ICs, but if their chip size is quite large, as reported to be, it could mean that the size of the internal conductors are larger, hence a lowering of I²R losses.

Yes?
No?

I agree.  This plus the lack of chip testing before mounting to the boards are the two things that concern me the most.  Here's why: yield.  There are two primary sources of yield loss (bad chips).

1) Process problems.  Ex: Too much etching of metal (opens), not enough etching of metal (shorts), and similar issues with other layers (transistors and layer interconnects).  These are usually noticed and/or fixed by the fab because they add test structures in between the chips in the scribe lanes and/or in unused areas of the chips.  During each step of the wafer production, they test these test structures to make sure that that particular step was done right.  If done wrong, the wafers are scrapped or sometimes the error can be corrected.  However, there can be a uniformity issue where the die on one part of the wafer are good, while all the die in another area are bad.

2) Random defects - figuratively (sometimes literally) "specks of dust" on the wafers.  Think of these this way.  Imagine putting a piece of graph paper on the wall (representing the wafer and the small squares are the individual die) and throwing darts at it randomly.  Lets say you throw 50 darts and the hole left by each dart represents a random defect.  If the graph paper has small squares (1000 per sheet of paper), then you have 50 bad die, 950 good die for 95% yield of good die.  Now imagine the squares (die) are 10x bigger so there are only 100 die per wafer.  Now 50 defects gives 50 bad die and 50 good ones for 50% yield.  Thus, larger die size impacts yield negatively.  Realize the numbers here were chosen for simplicity but the effect is VERY real. 

Small die --> high yields --> no chip testing --> probably good.
Large die --> low yields --> no chip testing --> not a good idea in my opinion.

ORSoC is relying on the concept of using a large number of cores per chip and turning off the bad ones.  The idea is that you can turn a bad die back into a good one.  This is generally an acceptable strategy and one that BFL is successfully using.  Depending on ORSoc's actual die size, the process yields, and the specific method of disabling cores, they might pull it off.  However as someone else mentioned in this thread, there are sometimes chips that are COMPLETELY dead - just a shorted blob of metal and completely worthless unless you want something to blow up power supplies.    Those really should be screened out at a minimum.  And if you're doing that, you might as well do a full chip test with binning.

Note: I'm not condemning the strategy that ORSoc is using.  It might work.  I would be a whole lot more comfortable if they were doing chip testing.

Disclaimer: I am a BFL customer.  I have not ordered any KnC product yet but I am seriously considering it.  If I had the cash on hand I might have already ordered.  Perhaps BTC I mine with my BFL hardware will go to KnC.

I thought I'd go ahead and load up on some Jupiters but the site says there's only 1652 left.  Anyone know how many have sold so far?  Genesis block said they already pre-sold 890 orders a few days ago -- at over 160 TH/s.  If they can deliver on all those orders, will that much processing power have any affect on the value of Bitcoins, or just on the mining profitability?

http://i43.tinypic.com/2qnmqs5.jpg

Why is everybody so happy that they can produce and deliver so many units per day?

Don't you realize this is a race, and the best way to maximize ROI for customers is to sell batches, as Avalon did?

Just think: if KnC sells 1,500 Jupiters and delivers them quickly, when added to the rest of the network each one will probably produce aprox. 1BTC or less per day, and ROI will be unlikely. If they sell +3,000 Jupiters (which seems likely they will do), when they arrive each Jupiter will produce 0,5BTC per day or less, and ROI won't never happen.

Honestly, it's pretty scary to see them pushing out those numbers. Each additional Jupiter they sell removes value from the previous one. Kinda the same problem we thought BFL would have, but the reality ended up being that they are so slow delivering that actually their very first customers may break/even with their units despite the delays.

and what is avalon doing?....they sale millions of avalon chips....it is the same thing

BFL sells chips, too. But only 100,000 https://products.butterflylabs.com/65nm-asic-bitcoin-mining-chip.html