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    Author Topic: Algorithmically placed FPGA miner: 255MH/s/chip, supports all known boards  (Read 119483 times)
    eldentyrell (OP)
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    felonious vagrancy, personified


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    September 07, 2012, 01:25:32 AM
    Last edit: September 07, 2012, 01:38:33 AM by eldentyrell
     #741

    Hrm im suffering from a strange issue


    java.io.IOException: you forgot to upload the bitstream to the FPGA


    You need to power-cycle the board while disconnected from USB.  In other words, unplug both the power and USB at the same time, then plug them back in.

    This is a "feature" of the ztex USB chip/code.  Stuff like this is the reason why I am so adamant about not throwing any more of my time down the black hole of debugging other peoples' proprietary USB interfaces.

    The printing press heralded the end of the Dark Ages and made the Enlightenment possible, but it took another three centuries before any country managed to put freedom of the press beyond the reach of legislators.  So it may take a while before cryptocurrencies are free of the AML-NSA-KYC surveillance plague.
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