I've started doing the detailed analysis on memory timing for Eth mining.
With tRRD=6, tRC=62, tCL=21 and 2000 mem clock, I can get almost 27Mh/s mining eth. Each hash takes 64 random DAG reads of 128 bytes each, and since they are random, each read should be from a different page. As well, the L2 cache hit rate should be near 0, so each DAG access requires a read from GDDR (2x32-byte reads from 2 GDDR chips).
Before reading, a page (row) has to be activated(opened), so 27Mh * 64 activate = 1728M activates per second. The Rx470/480 has 4 independent cache controllers, so a single GDDR5 chip will open 432M pages per second. With a 2Ghz mem clock, that's about 5 (4.73) clocks per activate. The closer that gets to 4, the better. Lower than 4 is not possible with Eth mining, since it takes 4 clocks to transfer 64 bytes (half a DAG entry). Note that if tRRD=6, means 6 clocks, some other timing factor is allowing the RAM to sustain <5 clocks per activate
I tried tRRD=5, and it only makes a small (~1%) improvement. That makes sense, since RRD is the delay between 2 activate commands when they are going to different banks. With only 16 banks, the memory controller has lots of opportunity to batch activate commands together in the same bank. However tRC is defined as, "The minimum time interval between two successive ACTIVE commands on the same bank". With tRC=62, the fastest access pattern would be to spread the accesses across different banks rather than batching them in the same bank.
So it seems I'm missing something about how the RAM timing. I know there are multiple clocks for GDDR5, and some run at double data rate (i.e. WCK). If tRRD=6 means six DDR address clocks, that would be 3 SDR command clocks (2Ghz is the command clock rate).
The GDDR5 specs refer to tRRDL (same bank group) and tRRDS (different bank group or bank groups disabled). Maybe what people are labeling tRRD is tRRDS, and some other data in the strap is tRRDL=4.
I tried reducing tRRD in SEQ_RAS_TIMING from 5 to 4, and don't see any improvement. I should be able to get ~29Mh with fully optimized timing at 2000 mem clock, but so far I can't get much more than 27.