Mine are correct. From a chip-design perspective, masking off the "unused" bits would actually add complexity. The simple, and most logical conclusion is that the fields can store larger values than are required by the specs for currently-produced GDDR5 RAM. I also suspect if anyone took the time to look at the JEDEC GDDR5 spec, you'd at least see tRP needs to support more than 5 bits (max 31).
To be 100% certain, on my Rx470 (Samsung K4G4) I changed MC_SEQ_MISC_TIMING: 0x09D82033
TRP_WRA=51 TRP_RDA=64 TRP=32 TRFC=157 Pad0=0
With my tweaked strap using 0x09D50CB3 I was getting 29.3Mh/s, and with only the high bit of RP_RDA and RP set, hashrate dropped to 23.1. I let it run for 15 minutes with those timings and it was stable.
I suspect for GCN1.2 devices (i.e. Tonga) that use the R9 SEQ_MISC format that RP_RDA is actually 7 bits, not 6 plus a 1-bit pad before tRP.
It is possible that we are both 'correct'.
The definition of MC_SEQ_MISC_TIMING in linux kernel is old
and corresponds to definition of MC_SEQ_MISC_TIMING in leaked(?) RAI register description file for Bonaire which is old too.
It is possible that definition of MC_SEQ_MISC_TIMING in newer architectures is different up to paddings.
