You may have to make tradeoffs for efficiency vs overclockability as well (i.e. switching frequency).  It's currently at 600khz (300 - 1500 khz is the range of possibilities).

Likewise i think the power inductor (0.36uH, <1.8mΩ) also leans more towards efficiency than ripple current

this might be more complicated though.. trading transient response for voltage stability and (lack of) noise

Yeah so looking over cooling options, it seems the most efficient would be, if possible, sandwich waterblock between Klondike boards, ideally between two K64's, to minimize # of blocks required.  But the heat from 128 chips to a common block might be too high.  Might be better to do K16x2 or K64x1

How about you move all this waterblock crap to another thread so we can stay on the topic of board design here?

Hello, I'm seeing in the K1 part list the GRM188R71E683KA01J marked capacitance as 6.8nF but in the datasheet is 68nF. Which one is needed?
Also the ERJ-3EKF2201V is marked as 1K Ohms and in the datasheet is 2.2K

That's weird. 6.8nF is correct and the Murata part# for 6.8nF is obsolete. So I've changed it to a Vishay VJ0603Y682KXXCW1BC instead. While checking that I noticed that the other 6.8nF in the schematic should be 10nF. I can't see any reason why I would have changed it to 6.8. So I've fixed that as well and to consolidate it with the 0.01uF on the oscillator I changed that one to 0603 instead of 0402 - so that double qty can be ordered of same part.

ERJ-3EKF2201V should definitely be ERJ-3EKF1001V - that was changed some time back and the part# didn't get changed with it. Thanks for finding these and pointing them out.

But also, two of those could end up being 470R instead of 1K. I'm still working on the result capture and it turns out that the result data rate is actually tied to the hash clock (apparently hashclk/128), which is idiotic IMO. So at higher clocks the pullup resistors may actually need to be 470R, and the capacitor lowered as well. Although when I tested 500R before it made little visible difference to rise time.

I'm was just pushing to higher clocks and couldn't figure out why it wasn't working until I scoped the result data again and saw that the bits are getting shorter, so much so that the delay circuit delays too much and the data never drops to "0". Geez. This also means rewriting the UART code to handle the nonce bytes more quickly by moving completion outside the ISR. I'm in the process of fixing this now.

BTW I did get a second ASIC mounted and have been battling with the stuff above. At first it had issues with 1.2V power shorting under the chip (hidden solder bridge), and after I reheated and bumped the chip a bit it cleared up. The nice thing is that I can say now that a short on the 1.2V doesn't blow anything or cause issues with the buck reg. It just shuts off without any drama. I had some issues with nonce range duplication due to testing on one bank when the code was written for interleaved banks - once I realized what was going on it was easy to adjust.

So it's running on both ASICs now and getting double the rate but I still can't go above about 180MHz until I change the result delay capacitor, which I don't want to do now at night. So tomorrow will get that switched out and see a faster capture signal. That should allow boosting the clock. The board is now mounted with thermal compound on a beautiful black heat sink sent to me for testing by steamboat. The chips are barely warm now.

Congrats on your progress BKK!

Regarding the previous statement, are you getting double the stated 333MH/s per chip or your getting double the rate that you had previously stated?

Most of the board except ASICs was done using stencil, hand place parts, toaster oven. The stencil was cut on my Silhouette SD. The toaster oven is a cheap 800W one worth about $25. I did a couple timing runs first with an empty board, my IR thermometer and a stopwatch, but I have no controller, so just measured temp and timed.

For the ASICs I used a toothpick to dab paste on the pads (well, more like along the pads in a line),  then placed the chip with tweezers, and then used a rework hot air gun to heat. First time I had a capacitor next to ASIC go tombstone again. So I got some kaplon tape and this time I placed little bits covering the other parts near by. I heat gently from about 10cm for 30 secs. Then I come in closer and heat the chip until the paste goes silver, and back off to 10-15cm for short time and then let it cool down.

So far I haven't done too badly but this isn't my forte really. I don't do it often so every time is a bit nerve wrecking as I worry about frying them. I think I've placed a bit too much paste each time so will cut back on the next one.

Not sure which previous statement. I only meant I'm getting double rate because now I have two chips installed. Same clock as before, but also better HW error rates now, though every now and then it blows a gasket and chunk of them pop up. I've been doing some testing with sending work data with clock cfg disabled but I'm not sure it helps. My theory was that every time I send data I'm sending clock cfg, so maybe that causes the PLL to re-lock. There is a bit that says "no chg clock this time", but I was distracted by other errors. Once I get further I'll try that again as maybe it will let the PLL stabilize more if not being updated with new cfg.

I have had it run at 220 MHz but it's not stable due to result capture timing I believe. It's actually saying about 330 MH/s when I run at 128 MHz, which is a bit high.

Also, I have a RasPi set up now and have been running the Erupter on that (off a hub). I'm just testing the Klondike there but seems like something is fishy. It worked earlier but I had a bunch of changes to pull over and it got muddled up. I expect I'll have that going soon.

Yeah there is a learning curve with reflow solder paste solder stencil etc.  I assume you were using Sn63PB37 solder?  That will have the lowest temp to reflow

It can be really tedious handplacing all the parts as well, and it has to be done within the working life of the paste

One thing that might be useful is to use the iron to apply heat directly to the pad on the opposite side of the asic, through the thermal vias.  this would reflow the thermal pad, but not the QFN pads

Yeah, the 'good ole' lead based solder is really amazing, especially compared to the RoHS solutions.. ugh.

they actually have pretty strict requirements 'by the book' for solder paste.  Stuff like "use within 6 months of purchase, keep refrigerated, use (reflow) it within 4 hours of application", but Sn63Pb37 is probably the most robust of all