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    Author Topic: Ultra Under-overclock image for A2 Innosilicon by Emdje - V5.0  (Read 79824 times)

    • emdje (OP)
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    August 24, 2014, 09:14:55 PM
     #41
    Quote from: forzendiablo on August 14, 2014, 03:26:59 AM
    Quote from: emdje on August 13, 2014, 05:09:06 PM
    Quote from: forzendiablo on August 13, 2014, 02:16:24 PM
    how can i edit IP of machine on windows? i cannot get ot my miner since its on 192.168.1.XX and i need it at *.0* Sad

    You can change that on the PI. Ssh into the PI and follow this tutorial: http://www.penguintutor.com/news/raspberrypi/linux-static

    For Ssh follow this:  https://learn.adafruit.com/adafruits-raspberry-pi-lesson-6-using-ssh/ssh-under-windows

    Hope this helps.

    Greetings Maarten

    thanx worked!
    decent OC here Smiley

    1300mhz running a2 at 90mhs+

    You are welcome. If you like to split your additional income because of the overclocking  Grin you are of course free to do so  Tongue : 1FiHCFcP4ovbV89nGhYEMWXSZsWnGUASSe

  • emdje (OP)
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    August 25, 2014, 08:42:44 PM
     #42
    Good news:
    Code:
    [2014-08-26 04:33:05] Started cgminer 3.9.0                   
     [2014-08-26 04:33:05] Run Reset=1                   
     [2014-08-26 04:33:05] ST MCU hardware reset start                   
     [2014-08-26 04:33:09] SPI Speed 4000 kHz                   
     [2014-08-26 04:33:09] ST MCU - Enable (Pre-header)                   
     [2014-08-26 04:33:09] A1 = 1320,4                   
     [2014-08-26 04:33:09] A1 PLL Clock = 1320MHz                   
     [2014-08-26 04:33:09] A1 = 1320,4                   
     [2014-08-26 04:33:09] A1 PLL Clock = 1320MHz                   
     [2014-08-26 04:33:09] A1 = 1300,5                   
     [2014-08-26 04:33:09] A1 PLL Clock = 1300MHz                   
     [2014-08-26 04:33:09] A1 = 1300,5                   
     [2014-08-26 04:33:09] A1 PLL Clock = 1300MHz                   
     [2014-08-26 04:33:09] A1 = 1300,5                   
     [2014-08-26 04:33:09] A1 PLL Clock = 1300MHz                   
     [2014-08-26 04:33:09] A1 = 1300,5                   
     [2014-08-26 04:33:09] A1 PLL Clock = 1300MHz                   
     [2014-08-26 04:33:09] AUTO GPIO CS                   
     [2014-08-26 04:33:10] spidev0.0(cs0): Found 8 A1 chips                   
     [2014-08-26 04:33:10] Found chip 1 with 54 active cores                   
     [2014-08-26 04:33:10] Found chip 2 with 54 active cores                   
     [2014-08-26 04:33:10] Found chip 3 with 54 active cores                   
     [2014-08-26 04:33:10] Found chip 4 with 54 active cores                   
     [2014-08-26 04:33:10] Found chip 5 with 54 active cores                   
     [2014-08-26 04:33:10] Found chip 6 with 54 active cores                   
     [2014-08-26 04:33:10] Found chip 7 with 54 active cores                   
     [2014-08-26 04:33:10] Found chip 8 with 54 active cores                   
     [2014-08-26 04:33:10] Found 8 chips with total 432 active cores                   
     [2014-08-26 04:33:11] spidev0.0(cs1): Found 8 A1 chips                   
     [2014-08-26 04:33:11] Found chip 1 with 54 active cores                   
     [2014-08-26 04:33:11] Found chip 2 with 54 active cores                   
     [2014-08-26 04:33:11] Found chip 3 with 54 active cores                   
     [2014-08-26 04:33:11] Found chip 4 with 54 active cores                   
     [2014-08-26 04:33:11] Found chip 5 with 54 active cores                   
     [2014-08-26 04:33:11] Found chip 6 with 54 active cores                   
     [2014-08-26 04:33:11] Found chip 7 with 54 active cores                   
     [2014-08-26 04:33:11] Found chip 8 with 54 active cores                   
     [2014-08-26 04:33:11] Found 8 chips with total 432 active cores                   
     [2014-08-26 04:33:11] SPI(cs2) no device                   
     [2014-08-26 04:33:11] ACK(cs2) timeout:cmd_RESET_BCAST-0.0336s                   
     [2014-08-26 04:33:11] SPI(cs3) no device                   
     [2014-08-26 04:33:11] ACK(cs3) timeout:cmd_RESET_BCAST-0.0321s                   
     [2014-08-26 04:33:11] SPI(cs4) no device                   
     [2014-08-26 04:33:11] ACK(cs4) timeout:cmd_RESET_BCAST-0.0314s                   
     [2014-08-26 04:33:11] SPI(cs5) no device                   
     [2014-08-26 04:33:11] ACK(cs5) timeout:cmd_RESET_BCAST-0.0322s                   
     [2014-08-26 04:33:11] A1 boards=2, active cores=864, Efficient=100%, speed=32.7M                   
     [2014-08-26 04:33:11] Probing for an alive pool                   
     [2014-08-26 04:33:11] Pool 2 difficulty changed to 32                                       
     [2014-08-26 04:33:11] Pool 1 difficulty changed to 512                                       
     [2014-08-26 04:33:11] Switching to pool 2 stratum+tcp://xxxxx - first alive pool                   
     [2014-08-26 04:33:11] Pool 1 stratum+tcp://xxxxx alive, testing stability                   
     [2014-08-26 04:33:11] Switching to pool 1 stratum+tcp://xxxxx                   
     [2014-08-26 04:33:11] Pool 0 stratum+tcp://xxxxx alive, testing stability                   
     [2014-08-26 04:33:11] Switching to pool 0 stratum+tcp://xxxxx                   
     [2014-08-26 04:33:11] Reconnect requested from pool 0 to xxxxx                   
     [2014-08-26 04:33:12] Pool 0 difficulty changed to 64                                       
     [2014-08-26 04:33:13] Network diff set to 261                                                             
     [2014-08-26 04:33:17] Network diff set to 28.5K                                                             
     [2014-08-26 04:33:17] API running in UNRESTRICTED read access mode on port 4028 (9)                   
     [2014-08-26 04:33:17] New block detected on network before longpoll                                       
    (5s):13.01K (avg):33.32Kh/s (pool):0.000h/s | A:0  R:0  HW:0  WU:0.0/m
     [2014-08-26 04:33:17] Accepted 01177391 Diff 234/64 BA1 0 pool 0                                       
     [2014-08-26 04:33:17] Accepted 75124b09 Diff 559/64 BA1 1 pool 0                                       
     [2014-08-26 04:33:18] Accepted 01207814 Diff 227/64 BA1 1 pool 0                                       
     [2014-08-26 04:33:18] Accepted ba2b3b60 Diff 352/64 BA1 1 pool 0                                       
     [2014-08-26 04:33:19] chip(cs0) 1: invalid nonce 0x8c303900                                                     
     [2014-08-26 04:33:19] Accepted e06f0d3d Diff 292/64 BA1 0 pool 0                                       
     [2014-08-26 04:33:19] Accepted 6e626f3c Diff 593/64 BA1 1 pool 0                     

    The miner can send work to 8 boards, I only have 2.
    But as you can see the 1320Mhz is accepted by the miner  Cool

    I will test some more, but this looks promising  Grin

    end of update

  • emdje (OP)
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    August 28, 2014, 08:43:10 PM
     #43
    New image uploaded. Device accepts the following values:
    1000
    1080-1200-1220-......1400 (increments of 20 MHz).


    ------Download link-------
    New download link for the image 2.0 (600Mb): https://mega.co.nz/#!GNMQAIrb!IjkpJvS36O29AfOKc_jR9aezdH5yZnHMiGY5mIGyypk

    You need 7zip to extract it. http://www.7-zip.org/
    ------Download link-------

    Please donate to 1FiHCFcP4ovbV89nGhYEMWXSZsWnGUASSe if you like my work and the effort I put into this.

  • BakSAj
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    August 29, 2014, 07:44:22 PM
     #44
    It can take 1220Mhz as effective? So its REALLY set as new frequency and not defaulted to 1200? Which cgminer binary is that? Thanks

  • emdje (OP)
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    August 29, 2014, 08:13:32 PM
     #45
    Quote from: BakSAj on August 29, 2014, 07:44:22 PM
    It can take 1220Mhz as effective? So its REALLY set as new frequency and not defaulted to 1200? Which cgminer binary is that? Thanks

    Yes it REALLY sets it as a new frequency! Look at post 42 (the first two frequencies, I only have an A2 mini). This was 1320Mhz, it takes that, but it takes the rest as wel.

  • BakSAj
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    August 29, 2014, 08:52:27 PM
     #46
    Quote from: emdje on August 29, 2014, 08:13:32 PM
    Quote from: BakSAj on August 29, 2014, 07:44:22 PM
    It can take 1220Mhz as effective? So its REALLY set as new frequency and not defaulted to 1200? Which cgminer binary is that? Thanks

    Yes it REALLY sets it as a new frequency! Look at post 42 (the first two frequencies, I only have an A2 mini). This was 1320Mhz, it takes that, but it takes the rest as wel.

    1320 was always possible as far as i remember. did you try e.g. 1220?

  • emdje (OP)
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    August 29, 2014, 09:40:10 PM
     #47
    Quote from: BakSAj on August 29, 2014, 08:52:27 PM
    Quote from: emdje on August 29, 2014, 08:13:32 PM
    Quote from: BakSAj on August 29, 2014, 07:44:22 PM
    It can take 1220Mhz as effective? So its REALLY set as new frequency and not defaulted to 1200? Which cgminer binary is that? Thanks

    Yes it REALLY sets it as a new frequency! Look at post 42 (the first two frequencies, I only have an A2 mini). This was 1320Mhz, it takes that, but it takes the rest as wel.

    1320 was always possible as far as i remember. did you try e.g. 1220?

    Just for you BakSAj  Wink:
    Code:
    [2014-08-30 05:36:53] Started cgminer 3.9.0                    
     [2014-08-30 05:36:53] Run Reset=1                    
     [2014-08-30 05:36:53] ST MCU hardware reset start                    
     [2014-08-30 05:36:57] SPI Speed 4000 kHz                    
     [2014-08-30 05:36:57] ST MCU - Enable (Pre-header)                    
    [2014-08-30 05:36:57] A1 = 1220,9                          <------
     [2014-08-30 05:36:57] A1 PLL Clock = 1220MHz         <------           
     [2014-08-30 05:36:57] A1 = 1240,8                         <------
     [2014-08-30 05:36:57] A1 PLL Clock = 1240MHz         <------    
     [2014-08-30 05:36:57] A1 = 1300,5                       
     [2014-08-30 05:36:57] A1 PLL Clock = 1300MHz                    
     [2014-08-30 05:36:57] A1 = 1300,5                    
     [2014-08-30 05:36:57] A1 PLL Clock = 1300MHz                    
     [2014-08-30 05:36:57] A1 = 1300,5                    
     [2014-08-30 05:36:57] A1 PLL Clock = 1300MHz                    
     [2014-08-30 05:36:57] A1 = 1300,5                    
     [2014-08-30 05:36:57] A1 PLL Clock = 1300MHz                    
     [2014-08-30 05:36:57] AUTO GPIO CS                    
     [2014-08-30 05:36:58] spidev0.0(cs0): Found 8 A1 chips                    
     [2014-08-30 05:36:58] Found chip 1 with 54 active cores                    
     [2014-08-30 05:36:58] Found chip 2 with 54 active cores                    
     [2014-08-30 05:36:58] Found chip 3 with 54 active cores                    
     [2014-08-30 05:36:58] Found chip 4 with 54 active cores                    
     [2014-08-30 05:36:58] Found chip 5 with 54 active cores                    
     [2014-08-30 05:36:58] Found chip 6 with 54 active cores                    
     [2014-08-30 05:36:58] Found chip 7 with 54 active cores                    
     [2014-08-30 05:36:58] Found chip 8 with 54 active cores                    
     [2014-08-30 05:36:58] Found 8 chips with total 432 active cores                    
     [2014-08-30 05:36:59] spidev0.0(cs1): Found 8 A1 chips                    
     [2014-08-30 05:36:59] Found chip 1 with 54 active cores                    
     [2014-08-30 05:36:59] Found chip 2 with 54 active cores                    
     [2014-08-30 05:36:59] Found chip 3 with 54 active cores                    
     [2014-08-30 05:36:59] Found chip 4 with 54 active cores                    
     [2014-08-30 05:36:59] Found chip 5 with 54 active cores                    
     [2014-08-30 05:36:59] Found chip 6 with 54 active cores                    
     [2014-08-30 05:36:59] Found chip 7 with 54 active cores                    
     [2014-08-30 05:36:59] Found chip 8 with 53 active cores                    
     [2014-08-30 05:36:59] Found 8 chips with total 431 active cores                    
     [2014-08-30 05:36:59] SPI(cs2) no device                    
     [2014-08-30 05:36:59] ACK(cs2) timeout:cmd_RESET_BCAST-0.0340s                    
     [2014-08-30 05:36:59] SPI(cs3) no device                    
     [2014-08-30 05:36:59] ACK(cs3) timeout:cmd_RESET_BCAST-0.0325s                    
     [2014-08-30 05:36:59] SPI(cs4) no device                    
     [2014-08-30 05:36:59] ACK(cs4) timeout:cmd_RESET_BCAST-0.0330s                    
     [2014-08-30 05:36:59] SPI(cs5) no device                    
     [2014-08-30 05:36:59] ACK(cs5) timeout:cmd_RESET_BCAST-0.0409s                    
     [2014-08-30 05:36:59] A1 boards=2, active cores=863, Efficient=99%, speed=30.0M                    
     [2014-08-30 05:36:59] Probing for an alive pool                    
     [2014-08-30 05:36:59] Failed to resolve (?wrong URL):80                    
     [2014-08-30 05:36:59] Pool 2 slow/down or URL or credentials invalid                    
     [2014-08-30 05:36:59] Pool 1 difficulty changed to 512                                      
     [2014-08-30 05:36:59] Switching to pool 1 stratum+tcp://xxxxx - first alive pool                    
     [2014-08-30 05:36:59] Pool 0 stratum+tcp://xxxxxxxxxxalive, testing stability                    
     [2014-08-30 05:36:59] Switching to pool 0 stratum+tcp://xxxxxxxxxxxxx                    
     [2014-08-30 05:36:59] Reconnect requested from pool 0 to xxxxxxxxxxxxxxxxxxxxx                    
     [2014-08-30 05:37:00] Pool 0 difficulty changed to 64                                      
     [2014-08-30 05:37:00] Network diff set to 235                                                            
     [2014-08-30 05:37:05] Network diff set to 28.1K                                                            
     [2014-08-30 05:37:05] API running in UNRESTRICTED read access mode on port 4028 (8)                    
     [2014-08-30 05:37:05] New block detected on network before longpoll                                      
    (5s):12.02K (avg):30.77Kh/s (pool):0.000h/s | A:0  R:0  HW:0  WU:0.0/m
     [2014-08-30 05:37:05] Accepted b8993e0b Diff 355/64 BA1 1 pool 0                                      
     [2014-08-30 05:37:05] Accepted b7e4d8bf Diff 356/64 BA1 0 pool 0                                      
     [2014-08-30 05:37:05] Accepted 014b4607 Diff 197/64 BA1 1 pool 0                                      
     [2014-08-30 05:37:05] Accepted a3f39325 Diff 399/64 BA1 1 pool 0                                      
     [2014-08-30 05:37:06] Accepted 01d60a79 Diff 139/64 BA1 0 pool 0                                      
     [2014-08-30 05:37:06] Accepted 01ac8489 Diff 152/64 BA1 1 pool 0                                      
     [2014-08-30 05:37:06] Accepted 014bd77a Diff 197/64 BA1 1 pool 0        

  • alpatcomm
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    August 30, 2014, 03:24:36 AM
     #48
    Hi Emdje,

    Youve been mentioned on the below link.

    Have you or anyone else on this thread, seen this article? http://cryptomining-blog.com/tag/innosilicon-a2-scrypt-asic-miner/

    Instructions here: https://github.com/MinerEU/scripta_a2#planning-feature
    Firmware Download here: https://mega.co.nz/#!t91g2BRK!qW2P1EeVZ_1M8QTHPjuEQWAgq-nK3Tlfgskl9itAo7A

    Cheers
    Alex
    1PjRuFuLYjRVXVq1yzFmfnrHKQdWsxR2By

  • emdje (OP)
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    August 30, 2014, 06:52:02 AM
     #49
    Quote from: alpatcomm on August 30, 2014, 03:24:36 AM
    Hi Emdje,

    Youve been mentioned on the below link.

    Have you or anyone else on this thread, seen this article? http://cryptomining-blog.com/tag/innosilicon-a2-scrypt-asic-miner/

    Instructions here: https://github.com/MinerEU/scripta_a2#planning-feature
    Firmware Download here: https://mega.co.nz/#!t91g2BRK!qW2P1EeVZ_1M8QTHPjuEQWAgq-nK3Tlfgskl9itAo7A

    Cheers
    Alex
    1PjRuFuLYjRVXVq1yzFmfnrHKQdWsxR2By

    I have seen more of the same article on different websites, but that is about the image I made before this one, where indeed only the values 1000, 1200, 1280, 1300 and 1400 were accepted.

    In this version the values 1000, 1080, 1200, 1220, 1240, 1260, 1280, 1300, 1320, 1340, 1360, 1380 and 1400 are accepted.
    However, this time it does not work to simply change the index.php file, you need the entire image: https://mega.co.nz/#!GNMQAIrb!IjkpJvS36O29AfOKc_jR9aezdH5yZnHMiGY5mIGyypk

  • alpatcomm
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    August 30, 2014, 07:49:43 AM
     #50
    Thanks Emdje

    Appreciate the feedback mate.

    cheers

    Alex
    1PjRuFuLYjRVXVq1yzFmfnrHKQdWsxR2By

  • alpatcomm
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    August 30, 2014, 08:50:16 AM
     #51
    oops, forgot to add..... One last question mate.

    Crytptalk mentioned the Scrypta OC firmware I have the link for, mentioned above, doesn't require extra cooling for the a2 chips because the firmware apparently controls the temperature of the a2 chips to prevent overheating.

    Question: Does your latest update to your firmware, do the same, so I won't have to build an airconditioner pipping assembly to feed the air con air straight to my miners intake fans?

  • BakSAj
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    August 30, 2014, 02:15:45 PM
     #52
    emdje: good job! where did you get the cgminer binary, if I may ask? Might be cool if voltage can be increased.

  • emdje (OP)
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    August 31, 2014, 05:24:49 AM
     #53
    Quote from: alpatcomm on August 30, 2014, 08:50:16 AM
    oops, forgot to add..... One last question mate.

    Crytptalk mentioned the Scrypta OC firmware I have the link for, mentioned above, doesn't require extra cooling for the a2 chips because the firmware apparently controls the temperature of the a2 chips to prevent overheating.

    Question: Does your latest update to your firmware, do the same, so I won't have to build an airconditioner pipping assembly to feed the air con air straight to my miners intake fans?

    The temperature is controlled by decreasing the amount of work going to the processors.
    Just try it out, see what the hash rate (poolside) does and decide what to do.

  • emdje (OP)
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    August 31, 2014, 05:29:35 AM
     #54
    Quote from: BakSAj on August 30, 2014, 02:15:45 PM
    emdje: good job! where did you get the cgminer binary, if I may ask? Might be cool if voltage can be increased.

    Someone who makes mining hardware contacted me with a problem I might be able to help with. So we helped each other. I can't give anyone the source code, at least not yet. But I have seen nothing that indicates the voltage can be increased in the code. Seems all hardware.

  • alpatcomm
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    August 31, 2014, 05:56:19 AM
     #55
    Quote from: emdje on August 31, 2014, 05:24:49 AM
    Quote from: alpatcomm on August 30, 2014, 08:50:16 AM
    oops, forgot to add..... One last question mate.

    Crytptalk mentioned the Scrypta OC firmware I have the link for, mentioned above, doesn't require extra cooling for the a2 chips because the firmware apparently controls the temperature of the a2 chips to prevent overheating.

    Question: Does your latest update to your firmware, do the same, so I won't have to build an airconditioner pipping assembly to feed the air con air straight to my miners intake fans?

    The temperature is controlled by decreasing the amount of work going to the processors.
    Just try it out, see what the hash rate (poolside) does and decide what to do.

    Hear ya loud and clear mate. Thanks for the feedback. Appreciate it

  • emdje (OP)
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    September 01, 2014, 06:19:55 AM
     #56
    You are welcome.

  • BakSAj
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    September 01, 2014, 02:19:46 PM
     #57
    Quote from: emdje on August 31, 2014, 05:29:35 AM
    Quote from: BakSAj on August 30, 2014, 02:15:45 PM
    emdje: good job! where did you get the cgminer binary, if I may ask? Might be cool if voltage can be increased.

    Someone who makes mining hardware contacted me with a problem I might be able to help with. So we helped each other. I can't give anyone the source code, at least not yet. But I have seen nothing that indicates the voltage can be increased in the code. Seems all hardware.

    Understood you may have made some agreement, but altering cgminer without releasing the sourcecode to github is againts licence policy. At least I think so.

    Can you name changes that are made in comparison to original Innosilicon FW? E.g. community of A2 users desperately needs extranonce support in cgminer.

    Do I need to install whole new image or just copy over thevar/www directory? I wonder how this will perform on my 1st batch A2 - it can do 84Mhs on poolside now, running 1200 Mhz (1280 makes no good).

  • emdje (OP)
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    September 01, 2014, 03:14:13 PM
     #58
    I altered the driver, not the actual code of cgminer (and then compiled it).
    On page 16 from the programming manual http://www.usbminers.nl/Innosilicon_A2_PG_v120140424.pdf there is a column named: io_pll_fb_div. In that column there is a binary code which is related to the clock frequency. Only increments of 20Mhz are accepted otherwise the is_pll_fb_div becomes a comma separated number, and that can't be transformed to binary.
    So, I added the extra binary numbers to the driver, and 'paired' it to the dropdown menu you see in the browser (index.php)

    Because it is not a simple change of the index.php you need the whole image.

  • BakSAj
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    September 02, 2014, 07:28:26 PM
     #59
    Guys, just a noob question. Im not able to shutdown miner via SSH. Either 'sudo shutdown' or 'sudo poweroff' kills just the OS (disconnects SSH), but the miner keeps running. Any idea? Thanks.

  • Saucy
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    September 04, 2014, 11:07:15 PM
     #60
    does anybody know if this will work with the new A2 terminator mini, and with what frequency setting, if so?
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