The way I read this thread is that there are some credible devs looking for a business model that makes their work sustainable and profitable, more profitable than simply mining with their own secret sauce on their own expensive hardware.

There is the 'mining with dev fee' model and the hardware provider model. Both models require popular acceptance and adoption of fpga mining to work. Early adopters take a lot of risk because of the high cost of getting started with fpga mining equipment and missing proof of acceptable ROI.

pollo e huevos ?

It'd be sweet if we had a coin whose proof of work algorithm was fpga and gpu friendly but asic resistant !

They have already developed it long time ago but the biggest problem thay are facing is how monetize it. I read somewhere that with FPGA it will be really easy to bypass claymore style fee. It is really easy to copy the design, something like that.

Start with something simple like SHA256D used in Bitcoin:

https://github.com/progranism/Open-Source-FPGA-Bitcoin-Miner

Or something from the official Xilinx marketing publication:

http://issuu.com/xcelljournal/docs/xcell_journal_issue_84/16

Have fun!

Edit: I forgot to include standard explanation about the difference between CPU programming and FPGA programming.

CPUs have von Neumann architecture with linear memory, e.g. from 0 to 4294967296. Compiling and running your first 10 line program will take seconds on your typical usable computer with 4GB of RAM.

FPGA have a completely generic two dimensional architecture that literally has kajilion of constraints. Most of those constraints are secret to the FPGA vendor. The XCVU9P FPGA discussed in this thread has about 2104 pads, just describing the pads that are actually connected with useful signals on the VCU1525 board is a file that has 25 pages in the manual. Those are the constraints that are visible and not secret.

When compiling your first 10 line FPGA program the Xilinx toolchain will still have to process those constraints even if you use less than 1% of 1% of the whole VCU9P chip. On the other hand the small XC7A35T chip on the training board has much, much less internal constraints that needs to be read by the toolchain.

You will observe that your small 10 line FPGA program will be completely compiled and done for a small device like like 7A35T while for the large device the Xilinx toolchain is still decrypting the secret VU9P constraints file. Amazon recommends that you run their FPGA development kit for VCU9P on a computer with 32GB of RAM to get sensible performance for nontrivial programs.

Just be aware of the above.

Edit2: Trying to learn logic design on a high-end device may seriously test your patience. Start with a low-end device.

Edit3: Grammar fixes.

Yes, it's basically lyra2rev2 with only a single round of cubehash and no memory. I'd guess maybe 900mh/s-1.2gh/s.

Edit: No, sorry, it's nist5 + bmw, luffa and cube. And a randomized order to the hashes. Ya, maybe 900Mh/s with some intelligent buffering. It also depends on how long the chain is, and I'm not quite sure I understand that.

Right now I'm reading a couple of books, watching youtube video's and using the information given here.  For others reading 'DIY FPGA' in the title and expecting to do it themselves.  Intel are giving away 'fpga for dummies' if you sign up for their spam at https://plan.seek.intel.com/PSG_WW_NC_LPCD_FR_2018_FPGAforDummiesbook.

Was hoping to use the AWS F1 instance with their fpga dev ami that has Xilinx SDx 2017.4, Free license for F1 FPGA development, but it sounds like that will be jumping in at the deep end.

I saw a Keccak fpga project for Nexys 4 Artix-7 boards, it says that it uses an external frequency generator at 100Mhz and has a performance of 100Mh/s.
 https://github.com/0x2fed/FPGA-Keccak-Miner

Lastly, I am not seeing anything on Amazons ToS that forbids mining, senseless says he does (or has done) it yet the o.p. and others have said Amazon will ban you for it.  I'll make that bet and report back if I can ever get or build a working AFI (bitstream).

Also from there:

http://pascalproject.com/features.html

15x 1080 performance, almost all algorithms. But not timeline...

Do you really think that they have in that box a single chip dissipating 1kW with 2 USB, 1 Ethernet and 1 HDMI port?