I hate to nag, but do you have any plans to release this bitstream or sell it? I am willing to offer my first born child. Thanks.

Yes, I think I've finally come up with a strategy that will make everyone happy.  It will be released, but it won't be free.  Stay tuned; I expect to make an announcement by the end of the month.

I think he's hinting at us getting him one these



Subscribed.

Spartan6 have a nice feature called chip DNA. It's unique 56 bit number. Device can read this, user thru JTAG also can read this. So, little program that read DNA thru JTAG and send this to server. Server makes personalized bitstream for that DNA and waits for payment. When payment is recived sends bitstream to buyer. That particular bitstream will only work with particular chip. And every one is happy, copying almost impossible.

That wouldn't make me happy though. I'm not really interested as much in the product of your work as in your work itself.
That is the source code of the program you used to place the elements.

I would pay for that, more that for a bitstream too.
But that is for you to decide if you wanna go this far.

Modifying bitstream without HDL code or schematic it's not that easy. Skilled programmist may easily read dissasembled code but reading bitstream it's different story. I didn't try and I don't know that PlanAhaed can create schematics from bitstream?

No, the DNA register isn't useful for copy protection.   I use it to
keep track of which chips got which error rates at which
frequency/voltage, but not much else.

The DNA register is just a shift register, so if you can get the
design into fpga_editor all you have to do is disconnect two wires and
hook it up to an SRL32 instead; then you can make the design think the
chip has any DNA code you like.

I don't think Xilinx gives you a tool that turns .bit files into .ngc
files that fpga_editor can load, but I also wouldn't be surprised if
somebody else has written one.

Here's the map output for the 9-May-2012 design:


Slice Logic Utilization:
  Number of Slice Registers:                79,020 out of 184,304   42%
    Number used as Flip Flops:              79,020
    Number used as Latches:                      0
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                     74,176 out of  92,152   80%
    Number used as logic:                   67,312 out of  92,152   73%
      Number using O6 output only:          21,802
      Number using O5 output only:             126
      Number using O5 and O6:               45,384
      Number used as ROM:                        0
    Number used as Memory:                   4,960 out of  21,680   22%
      Number used as Dual Port RAM:              0
      Number used as Single Port RAM:            0
      Number used as Shift Register:         4,960
        Number using O6 output only:           320
        Number using O5 output only:           480
        Number using O5 and O6:              4,160
    Number used exclusively as route-thrus:  1,904
      Number with same-slice register load:  1,904
      Number with same-slice carry load:         0
      Number with other load:                    0
Slice Logic Distribution:
  Number of occupied Slices:                18,734 out of  23,038   81%
  Nummber of MUXCYs used:                   29,856 out of  46,076   64%
  Number of LUT Flip Flop pairs used:       74,786
    Number with an unused Flip Flop:        15,383 out of  74,786   20%
    Number with an unused LUT:                 610 out of  74,786    1%
    Number of fully used LUT-FF pairs:      58,793 out of  74,786   78%
    Number of unique control sets:              65
    Number of slice register sites lost
      to control set restrictions:             228 out of 184,304    1%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                         1 out of     338    1%
    Number of LOCed IOBs:                        1 out of       1  100%

Specific Feature Utilization:
  Number of RAMB16BWERs:                         0 out of     268    0%
  Number of RAMB8BWERs:                          8 out of     536    1%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       5 out of      16   31%
    Number used as BUFGs:                        5
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     3 out of      12   25%
    Number used as DCMs:                         0
    Number used as DCM_CLKGENs:                  3
  Number of ILOGIC2/ISERDES2s:                   0 out of     586    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     586    0%
  Number of OLOGIC2/OSERDES2s:                   0 out of     586    0%
  Number of BSCANs:                              1 out of       4   25%
  Number of BUFHs:                               0 out of     384    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFHs:                               0 out of     384    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                           14 out of     180    7%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       4    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            3 out of       6   50%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            1 out of       1  100%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%

  Number of RPM macros:          293
Average Fanout of Non-Clock Nets:                2.25

Peak Memory Usage:  3113 MB
Total REAL time to MAP completion:  47 mins 20 secs
Total CPU time to MAP completion:   47 mins 16 secs

Hmm so vs current speeds (200MH/s ?) that extra 45MH/s (22.5% ?) will take 38 days (at current difficulty) to earn 1BTC
So is the pricing per mining device or a per user price?

Deal. You send me the bitstream, and I'll get you a new taillight for the Kia.