That seems to say on actual silicon they could only achieve 240MH/s (which is still quite good).
Very interesting read and if I am reading right they actually achieved 300MHs..
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Achieved resultThen we got following clock from Trace timing analysis tool - 2.968 ns design performance limitations. That's pretty cool - means 337 Mhz clock. You can view timing report by clicking here. And in our first prototype things seemed to work, but we have not analyzed error rates. When we have finished implementation of communication protocol with computer and measured error rates,
we got bad luck, as with low error rates (below 0.5%) it functions only at 240 Mhz at core voltage 1.25 V (giving about 300 Mh/s and consuming acout 12W), and it still functions at 290 Mhz, but error rate is so high - about 85% of cores are giving errors. Also interesting detail, that if we strip and remove half of rounds, then it works at 290 Mhz well. 300 Mhz @ 1.25 V core voltage is undoable because of random hangs.
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